MAX10 - Family Overview Training

MAX10 - Family Overview Training

Confidential Material MAX 10 FPGAs - Overview Tom Schulte Low Cost Product Marketing 5/9/2014 Innovation Leader Across the Board PLDs Lowest Cost, Lowest Power FPGAs FPGAs Cost/Power Balance Mid-range FPGAs SoC & Transceivers SoC & Transceivers FPGAs Optimized for High Bandwidth PowerSoCs High-efficiency Power Management RESOURCES Embedded Soft and Hard Processors Design Software Development Kits Intellectual Property (IP) Industrial Computing Enterprise 2 Low Cost Families Altera Continues Focus & Investment More performance, features, or density FP G t c u rod P A Cyclone

Cyclone VV SoC SoC s Next Generation Cyclone Cyclone VV Cyclone Cyclone IV IV Cyclone Cyclone III III Cyclone Cyclone IIII Cyclone Cyclone L CP 2000 du o r DP MAX MAX IIII MAX MAX 10 10 c ts MAX MAX VV 2013 ng n i r e io v t i l a De ener s G t

t c x Ne Produ Future In Design Product Planning 3 MAX 10 FPGAs: Revolutionizing Non-Volatile Integration FPGA Capabilities - Non-volatile Features - 4 Up to 50,000 Logic Elements Analog Block with ADC Internal SRAM PLLs DSP Blocks External Memory Interface (e.g. DDR3) Dual Image Configuration Nios II Embedded Processor LVDS, PCI, and 30+ other I/O Standards Design Security Sleep Mode Instant-On User Flash Memory Voltage Regulator Internal Oscillator MAX 10 FPGAs Simplify FPGA Systems Traditional FPGA MAX 10 FPGAs Vsupply Vsupply LDO LDO LDO 3.3V 1.2V 2.5V 3.3V

Dual Image Configuration Device Traditional FPGA 3.3V I/O Dual Image Configuration Memory (Up to 50k LE) MAX 10 FPGA 3.3V I/O (Up to 50k LE) Analog ADC Standard Configuration Time 5 Analog Analog Block Instant-On Configuration MAX 10 FPGAs Increase Capabilities of CPLD Systems External Memory Interface Analog Analog User Flash 3.3V I/O (Nios code) 3.3V I/O CPLD MAX 10 FPGA DSP Single Image Single

Image Dual Image CPLD MAX 10 FPGAs 240 8,000 2,000 50,000 Single Dual DSP No Yes DDR3 SDRAM No Yes Analog Block w/ADC No Yes Embedded Processor No Nios II Logic Elements Instant-On Images 6 Block MAX 10 vs. Prior Family Higher Single Chip Integration Feature MAX V CPLDs MAX 10 FPGAs 180 nm

55 nm 2,000 LEs 50,000 LEs Single Image Dual Image, AES User I/O 271 Up to 500 User Flash Memory 8 Kb Up to 512 Kb - Embedded RAM, DSP, ADC, PLL No Yes Process Technology User Logic (max.) On-chip Configuration On-chip hard IP blocks Remote System Upgrade Lowering System Cost & Increasing Reliability 7 MAX 10 FPGA - Floorplan DSP Blocks Main Architecture Modules - Logic array - On-chip RAM & FLASH RAM Blocks Analog Blocks

- DSP blocks Config. Flash - Up to two analog blocks User Flash - Up to eight I/O banks Control Block - Up to four PLLs - Oscillator & Clocks - Soft IP functionality Nios II 32-bit processor, Ethernet MAC, PCIe MAC, Video IP Suite, etc. 8 Logic Array External Blocks Memory Interfaces PLLS MAX 10 FPGA Family Plan Block User 18x18 Memory Flash 1 Mults PLLs Internal Config. (Kb) (Kb) External RAM I/F Device LEs 10M02 2,000 108 96

16 1, 2 Single - Yes 2 10M04 4,000 189 128 19 1, 2 Dual 1, 1 Yes 2 10M08 8,000 378 256 24 1, 2 Dual 1, 1 Yes 2 10M16 16,000 549 256 45 1, 4

Dual 1, 1 Yes 3 10M25 25,000 756 256 61 1, 4 Dual 2, 1 Yes 3 10M40 40,000 1,260 512 125 1, 4 Dual 2, 1 Yes 3 10M50 50,000 1,638 512 144 1, 4 Dual 2, 1

Yes 3 Notes: 1. Additional User Flash may be available, depending on configuration options. 2. SDR SDRAM or SRAM only. 3. SDR SDRAM, SRAM, DDR3, DDR2, or LPDDR2. 4. ADC blocks available on die but may not be available in low pin count packages. 9 ADC 4, TSD Preliminary and subject to change without notice. MAX 10 FPGA - Feature Set Options Feature Set C: Compact F: Flash A: Analog Yes Yes Yes Dual Image w/Remote System Upgrade - Yes Yes Analog Features Block - - Yes Single Image C F Three Feature Set Variants To Order From

10 A Package Plan & Available I/O (Dual (Dual Power Power Supply: Supply: 1.2V/2.5V) 1.2V/2.5V) Product Line 10M02 10M04 10M08 10M16 10M25 10M40 10M50 D D D D D D D 81-WLCSP 36-WLCSP 3x3mm2 4x4mm2 0.4mm Pitch 0.4mm Pitch C (27) C/F (56) - 256-FBGA 17x17mm2 1.0mm Pitch 324-UBGA 15x15mm2 0.8mm Pitch C/F/A (178) C/F/A (178) C/F/A (178) C/F/A (178) C/F/A (178) C/F/A (178) C (160) C/F/A (246) C/F/A (246) C/F/A (246) - Note: Selected items = Pro-active automotive p/n rollout.

Other product line/package combinations available upon request & sufficient ROI. 484-FBGA 672-FBGA 23x23mm2 27x27mm2 1.0mm Pitch 1.0mm Pitch C/F/A (250) C/F/A (320) C/F/A (360) C/F/A (360) C/F/A (360) C/F/A (380) C/F/A (500) C/F/A (500) Preliminary and subject to change without notice C: Compact F: Flash Bare Die WLCSP xBGA A: Analog U = 0.8mm ball spacing F = 1.0mm ball spacing Wide Variety of Sizes & Available I/O 11 Package Plan & Available I/O (Single (Single Power Power Supply: Supply: 3.3V) 3.3V) Product Line 10M02 10M04 10M08 10M16 10M25 10M40 10M50 S S S S S S S

144-EQFP 16x16 mm2 0.4 mm Pitch C (101) C/F/A (101) C/F/A (101) C/F/A (101) C/F/A (101) C/F/A (101) C/F/A (101) 153-MBGA 8x8mm2 0.5mm(1) C (112) C/F/A (112) C/F/A (112) - Notes: 1 Easy PCB utilizes 0.8mm PCB design rules 2 - Items in blue = Pro-active automotive p/ns. Others available upon request & sufficient ROI. 169-UBGA 11x11mm2 0.8mm C (130) C/F/A (130) C/F/A (130) C/F/A (130) - Preliminary and subject to change without notice C: Compact F: Flash A: Analog Bare Die EQFP xBGA M = 0.5mm ball spacing U = 0.8mm ball spacing Single Supply Option for Simplicity & Convenience 12 MAX 10 FPGA Ordering Information Family Optional Suffix

10M: MAX 10 FPGA ES G = RoHS 6 P = Leaded = Special processing 10M 16 x x u484 i 7 x Product Line 02: 2K LEs 04: 4K LEs 08: 8K LEs 16: 16K LEs 25: 25K LEs 40: 40K LEs 50: 50K LEs Speed Power Supply S: Single Voltage D: Dual Voltage Feature Option C: Compact features F: Flash features A: Analog features Package Type & Ball Count V: Wafer level chip-scale E: EQFP M: MBGA U: UBGA F: FBGA 36, 81 144 153 169, 324 256, 484, 672 13 6, 7, 8 6 = fastest, 8 = slowest Grade / Temperature C: Commercial (TJ = 0C to +85C) I: Industrial (TJ = -40C to +100C) A: Automotive (TJ = -40C to +125C) MAX 10 FPGA I/O Standard Support

I/O Standard Single-Ended External Memory Interfaces (& Voltage Referenced I/O) LVDS 14 Variant LVTTL/LVCMOS 3.3V LVTTL/LVCMOS 3.0V LVTTL/LVCMOS 2.5V LVTTL/LVCMOS 1.8V LVTTL/LVCMOS 1.5V LVTTL/LVCMOS 1.2V PCI Schmitt Trigger (RX only) SSTL2 Class I SSTL2 Class II SSTL18 Class I SSTL18 Class II SSTL15 Class I SSTL15 Class II SSTL15 SSTL135 HSUL12 HSTL18 Class I HSTL18 Class II HSTL15 Class I HSTL15 Class II HSTL12 Cass I HSTL12 Class II Dedicated LVDS (RX/TX) 3 Dedicated Mini-LVDS (TX) 3 Dedicated RSDS (TX) 3 Dedicated PPDS (TX) 3 External Resistor LVDS (TX) External Resistor Mini-LVDS (TX) External Resistor RSDS (1R) (TX) External Resistor RSDS (3R) (TX) External Resistor PPDS (TX) LVPECL (RX only) BLVDS (RX/TX) Toggle Rate 1 (MHz) 250 250 250 250 200 250 200 250

250 300 300 300 300 300 300 200 300 300 300 300 200 200 830/800 Mbps 380 Mbps 340 Mbps 420 Mbps 600 Mbps 380 Mbps 170 Mbps 342 Mbps 420 Mbps 830 Mbps 830/475 Mbps Max Strength 2 mA 16 mA 16 mA 12 mA 8 mA 8 mA 12mA/50 W 16 mA/25 W 12mA/50 W 16 mA/25 W 12mA/50 W 16 mA/25 W 34 W 34 W 34 W 12mA/50 W 16 mA/25 W 12mA/50 W 16 mA/25 W 12 mA/50 W 14 mA/25 W 16 mA Load 10 pF 10 pF 10 pF 10 pF 10 pF 10 pF 10 pF

7 pF 7 pF 7 pF 7 pF 7 pF 7 pF 7 pF 7 pF 7 pF 7 pF 7 pF 7 pF 7 pF 7 pF 7 pF 6 pF 2 6 pF 2 6 pF 2 6 pF 2 6 pF 2 6 pF 2 6 pF 2 6 pF 2 6 pF 2 6 pF 2 6 pF 2 Application General purpose General purpose General purpose General purpose General purpose General purpose General purpose General purpose DDR1 DDR1 DDR2 DDR2 DDR3 DDR3 DDR3 DDR3L LPDDR2 DDR2+/QDR2+/RLDRAM2 DDR2+/QDR2+/RLDRAM2 DDR2+/QDR2/QDR2+/RLDRAM2 DDR2+/QDR2/QDR2+/RLDRAM2 General purpose General purpose Notes: 1. Toggle rate (maximum) assumes max. drive strength, fastest slew rate setting for the specified load, and fastest speed grade (c6).

2. Measured on a single pin, not pair. 3. Only available on the bottom I/O banks (Bank3, Bank4). 3 Early Access Programs for MAX 10 FPGA 2013 2014 Jul. Aug. Sept. Oct. Nov. Dec. Jan. Feb. Mar. Apr. May Jun. Jul. Aug. Sept. Oct. Nov. Dec. #1 - EIP Rev. MAX 10 FPGA Device Handbook 13.1 #2 - ESP Rev.

Rev. 14.0 14.1 #3 - EDP Early Information Program Unlimited # of customers Monthly bulletins Advanced Info. Brief Preliminary handbook Other specials 15 Early Software Program Early Device Program Limited # of customers Hidden S/W in v13.1 (10M08 only) Production S/W in v14.0 (all devices) Compilation & early timing EPE Limited # of customers ES and/or EAP device shipments 10M04, 08, 40, and 50 ES p/ns Early .POF / .SOF support MAX 10 FPGAs Summary MAX 10 FPGAs revolutionize non-volatile integration - Single-chip, non-volatile solution with the smallest footprint Only dual-persona single-ship, non-volatile solution Integrated ADC and other system-cost saving hard IP Up to 95% dynamic power savings via sleep mode Ideal for both datapath and control plane applications MAX MAX 10 10 FPGA FPGA Devices Devices

FPGA 16 Non-Volatile Whats Next? 1H 2014 Early Information Program 2H 2014 Devices & Dev Kits Shipping Would you sign-up for monthly email updates on MAX 10 FPGAs (with valid NDA)? 17 Confidential Material Back-Up Information MAX 10 FPGA M153 Package Easy PCB Footprint Intentionally created gaps in ball grid array to allow space for PCB traces and/or through-hole vias. 8mm Goal: Easy PCB board design 1. Use 0.8mm pitch design rules instead of 0.5mm rules. 2 layer signal breakout (SMD on both component and PCB) 3 mil line/space 16 mil PTH Shared P/G PTH 2. Avoiding use of blind or buried vias. 0.5mm 3. Minimize the number of PCB layers needed to route to all device pins. 8mm Note: Altera recommended PCB layout (preliminary) in 4Q 2013 19 Click to return to page 13 Thank You

Recently Viewed Presentations

  • ESnet Defined: Challenges and Overview Department of Energy ...

    ESnet Defined: Challenges and Overview Department of Energy ...

    The ESnet Approach for Required Capabilities User experience in the first year of OSCARS operation has revealed several new capabilities that are required The usefulness of permitting over subscribing a path is needed to accommodate backup circuits allow for site...
  • What is Geography?

    What is Geography?

    I like Pat Gober's definition because it clarifies that geography is NOT factoids: the highest mountains, the longest rivers, capitals of nations, etc. Instead, it is the spatial organization of human activity and natural processes on Earth. If it is...
  • Stable Isotopes  Physical Fundamentals 9/27/12 Lecture outline: 1)

    Stable Isotopes Physical Fundamentals 9/27/12 Lecture outline: 1)

    equilibrium fractionation kinetic fractionation mass-independent fractionation spectrometer light intake Annual layers in a tropical ice cap Introduction to Stable Isotope Geochemistry Stable Isotope geochemistry is concerned with variations of the isotopic compositions of elements arising from physicochemical processes (vs. nuclear...
  • Richard Simon-Lewis - Cayman Islands

    Richard Simon-Lewis - Cayman Islands

    Richard Simon-LewisHead of Origination, Client Coverage, Marketing & Communications, UKEF. ... working with colleagues in DIT, DFID, FCO, HMT and other departments in the UK and overseas. ... We can support Project or Structure Finance deals as well as Public...
  • Development of Islamic Windows of Conventional Banks: Global ...

    Development of Islamic Windows of Conventional Banks: Global ...

    İslami Finansın Birleşik Krallık'ta Gelişimi. Professor Humayon Dar. Yönetim Kurulu Başkan, Başkan & CEO. Edbiz Consulting Ltd. 'Edbiz Danışmanlık Ltd.) [email protected]
  • Principles of Operations Management "JUST WHAT IS OPERATIONS

    Principles of Operations Management "JUST WHAT IS OPERATIONS

    "What is Operations Management" by Tony "Z" Zampello CSCP CPIM CIRM. Agenda. ... Full mid-term and final exam test databanks for each book. Predesigned Microsoft Excel spreadsheets to illustrate complex models and "what-if" scenarios.
  • Outline Of Todays Discussion 1. Monocular & Binocular

    Outline Of Todays Discussion 1. Monocular & Binocular

    A fundamental problem in perception: How do we recover a 3-d world from a 2-d retinal image? A . Monocular Depth Cue. is information . about . depth (i.e., relative position along the "Z" axis) that is available even in...
  • Ionic Compounds - MR. Hill's class

    Ionic Compounds - MR. Hill's class

    Naming compounds containing polyatomic ions. If there is a formula which contains more than two elementsyou must go to the chart of polyatomic ions on Pg.4 of your Data booklet to determine the polyatomic ion(s) in the formula and the...