Current status and Future plans of ALICE-FoCAL

Current status and Future plans of ALICE-FoCAL

1 Current status and Future pl st status and Future plat status and Future plus and Future pl Fut status and Future plure pl ans of ALICE FOCAL Project ALICE FOCAL Project FOCAL Project status and Future pl Taku Gunji Center for Nuclear Study University of Tokyo For the ALICE-FOCAL Team 2 Outline Collaboration Summary of physics and measurements Requirements of the FOCAL Conceptual Detector Design Current R&D Status Future Plans Summary 3 Collaboration

Center of Nuclear Study, University of Tokyo, Japan Variable Energy Cyclotron Center, Kolkata, India Institute for Subatomic Physics and Nikhef, Utrecht University, Nethe rlands Bergen University, Bergen, Norway Czech Technical University, Prague, Czech Republic ORNL, Oak Ridge, US University of So Paolo University of Jyvskyl, Finland Yonsei University, Seoul, Republic of Korea More participation from China/Korea are very welcome!! 4 Physics Motivation of ALICE-FOCAL Main physics topics: Gluon saturation (pA) Fully exploit the opportunity at the LHC to access smaller-x region & large saturation scale by going to forward rapidity. RHIC forward rapidity (h=3) LHC mid-rapidity. Importance to u nderstand initial state effects at the LHC (pA). Thermalization mechanism (saturation glasma) (AA) Systematic measurements of hot and dense medium (AA) Elliptic flow/ridge/jet quenching (AA) Provide forward (h>3) coverage for identified particle me asurements EM calorimeters for (prompt) g, p0, h, heavy quark(onia), jets, a nd correlations (with rapidity gaps) Requires high granularity (lateral and longitudinal)

5 FOCAL Location and Plans Stage 1 (z=3.5m, 2.5

Ng is dominated (95%) by low pT(<1GeV) g Particle density (HIJING p+A) # of g in FoCAL in central p+Pb (Pb going direction) pT>0.5 pT>1 7 Requirement of the FOCAL Requirements of the FOCAL High granularity to cope with high multiplicity environment Adequate x and y position resolution, and energy resolution Adequate Level-0 trigger generation Adequate rejection of charged hadrons Favored technology: W+Si sampling calorimeter Readout: Si Pad (~1x1cm2)/Si Strip/Si pixel (~0.1x0.1mm2) Readout Pros Cons Pad

Good energy resolution trigger capability double-hit resolution, occupancy, dynamic range Strip Excellent position resolution, energy resolution Ambiguities for high multiplicity, occupancy, ghost pairs Pixel Excellent position resolution, High multiplicity Huge # of channels, smaller bits, slow for readout (usually need L0 trig.) 8 Conceptual Detector Designs Design-I Standard W+Si (pad/strip) sampling calorimeter Similar to the PHENIX FOCAL but 3.5m away from IP Pad readout for energy measurement. Pad size ~ Molier radius Strip in preshower stage for position measurement.

Design-II W+Si pixel sampling calorimeter Idea from Si pixel detector utilized as tracking device Pixel size ~ 0.05x0.05, 0.1x0.1mm2 Monolithic Silicon Sensors [MAPS] (MIMOSA, LePix, SoI, etc) Readout only 1 bit Design-III Possible combination of (I)+(II) Pad + pixel (preshower) readout. Pixel size ~ 0.1x0.1, 0.5x0.5, 1x1 mm 2 9 Working Items and Main Players Design-I/Design-III Simulation CNS/Prague (features) VECC (clustering) Construction/Mechanics CNS (Si/W/(Mechanics)) Prague (Mechanics) ASICs CNS ORNL

Digital/DAQ None Hope to collaborate with EMCal/DCal colleagues. Design-II Simulation Utrecht MAPS Strasborg (MIMOSA) Construction/Mechanics Utrecht DAQ Bergen 10 Conceptual Detector Design-I Standard W+Si (pad/strip) calorimeter First segment CPV

Second segment Si Strip (X-Y) Tungsten Third segment Si pad Single sided Si-Strip (2X0-6X0) 2g separation, 6 inch wafer wafer size: 9.3cmx9.3cmx0.525mm 0.7mm pitch (128ch/wafer) Si pad size: 1.1x1.1cm2 (64 ch/wafer) W+Si pad : 21 layers 3 longitudinal segments My personal interests to replace Summing up raw signal strip to pixel (1x1mm2 or 0.5x0.5mm2) longitudinally in one segment W thickness: 3.5 mm (1X0) T. Tsujis talk 11 Detector Performance (Simulation) Detector simulation linearity

<1% up to 200GeV Resolution: 22%/sqrt(E) + 1.6% Position resolution by the strips at 4, 5, and 6 layer. Resolution ~ 0.25mm with 0.7mm pitch T. Tsujis talk 12 p0 Reconstruction (Simulation) Single p0 reconstruction Left: pi0 reconstruction efficiency by pads (inv. mass) Right: pi0 reconstruction efficiency by strips & pads (energ y vs. 2 gamma distance) Full simulation (p+p/p+Pb) by T. Tsuji. Efficiency >50% for E<50 GeV Tw sta o g r t am to m be a c m lus

er te ge r s d Efficiency > 50% for E>60 GeV Quarkonia Reconstruction (Simula tion) Quarkonia simulation Mass resolution: 4% for J/y and 3% for U Full simulation will be done. 13 14 Clustering Study (VECC) Development of clustering logic (VECC) Data cleanup with a small Edep(ADC) threshold Clustering of showers by newly developed Dynamic FCM (dFCM) 2-3mm separation can be achieved. (p0 E>200 GeV) 340 7 1.29

320 y cellid 300 280 260 240 220 71 16.76 57 12.32 180 160 200 42 12.73 78 16.82 77 22.39 200

220 2 0.098 240 Embed 4 gammas with 5mm separation. Cluster reconstructed based on the dynamical fuzzy c-mean Method (d-FCM). 260 Legend Data count 29 4.55 280 300 x cellid Future pl 320 340 360

380 Total energy deposition in MeV 15 Composition Readout Flow Summing board: Assemble jig (1.5mm thickness) sum up signals in segments longitudinally, biases ASIC cards : Summing board Preamplifer + shaper (analog out) or QTC (digital out) ADC(12-14bit)/TDC(TMC)+FPGA board: Digitizer, ZS, feature extraction, formatting, trigger handling, buffering SRU (scalable readout unit):

Developed by RD51. Trigger handling, data format & transfer, master of sl ow control Summing board ADC/TDC/FPGA ASIC Fast analog/digital out for trigger? Scalable Readout Unit Optical out 16 Spec. of our Si pad/strips Production of pads/strips by HPK from 6 inch wafer. 25 Si pads and X strips are in our lab. QA was done by HPK. Pads: Cd=25-30pF, Id=2-10nA Picture of Si-Strip!! Size: 9.3x9.3 cm2 Thickness: 535mm Pad size: 1.1x1.1 cm2 Number of pads : 64 17

ASIC Development Pads readout : Dynamic range: 50fc 200pC . Cross talk < 1%. S/[email protected] R&D of the ASIC is being done by CNS+RIKEN/KEK and ORNL Dual charge sensitive preamplifier using capacitive division First prototype QTC (charge-to-time converter, no CMOS switches) 10pF High side C Dual transimpedance preamplifier 5.6nF 200pF CSA PZ high PZ Strip readout: Dynamic range: 4fc 2pC. PACE-III (CMS preshower, LHCf W+Si) Clow 560pF CSA 10pF Low side

ASIC Z = 1/wC + Zcf/A Discussion to use PACE-III has been started with CMS. Pixel readout: R&D of ASIC for pixels (1x1, 0.5x0.5mm2) is under discussion. S. Hayashis talk 18 Current Status of ASIC R&D Two types of prototype ASICs were designed. Dual CSP+shaper with capacitive division and Dual QTC Peaking time: tpeak ~ 2usec. Good linearity up to 200pC 1st Prototypes (TMC0.5um) will come to our lab. soon. Plan to develop for faster signal processing. high low 2.5use c S. Hayashis talk 19 Future ASIC Developments

Future ASIC developments Saturation avoidance circuit High gain (R=1kohm) Dual transimpedance amplifier QTC without CMOS switches CSP+shaper+(AMC+r-amp/ comparator+buffer)+MUX (Pixels) Input current (0.1pC-150pA) Low gain (R=0.1kohm) Output (high, 1kohm) (0.1pC-150pA) Output (low, 0.1kohm) (0.1pC-150pA) Under designing 20 Another Geometrical Idea hexagonal towers (ORNL)

fit nicely in circles around beam-pipe uses more silicon surface of cylindrical ing ot triangular pads and ASICs Bias resistors (100k) Coupling Cap (300pF) Cd = 30pF 3 Dec 10 3.3V NMOS 1000u/0.8u 100uA bias Detector: ~40pC charge out. 21 Conceptual Detector Design-II W absorber + Monolithic pixel sensor MIMOSA chips (digital readout) are promising to use. Development has been started.

20um pixel size 100 um pixel size (109 pixels) suppress data volume, reduce RO time avoid saturation . GBT/GBR being developed by CERN in the end CMOS wafer including thin sensitive volume and electronic layers charge from traversing particles collected at diodes FoCal Layer_0 MAPS_0 MAPS_15 E-Link ca. 15cm twisted pair cables @ 4,8 GHz 16 Clock Serial/ Deserial Control/Trigger MAPS_383

16 Clock GBTX 4.8 Gbit Fiberlink Vcsel Driver Data E-Link TLC12 GBLD_23 16 IC/ GBTSCA JTAG Slow Temp. Control Layer 0 FoCal Layer_23 MAPS_368 0-11

GBLD_0 GBTX 24 22 Ribbon fiber cable 12-23 TLC12 Ribbon fiber cable GBTIA Buffer Receiver To other layers 4.8 Gbit Fiberlink BackBox of Tower 0 16

Serial/ Deserial Control/Trigger Data IC/ GBTSCA JTAG Slow Temp. Control Layer 23 E-Link uses SLVS: Scalable Low Voltage Signaling (Low power / low voltage LVDS) All GBT chips are part of CERN Project (Gigabit receivers) MAPS readout 23 MAPS Open Questions and Possible Specs. pixel size: current designs 20 m for FoCal 100 m? charge collection? data volume: zero suppression?

full frame readout? possible option: GBTX serializer per layer, 4.8 GB/s output via t wisted pair option worked out power consumption: currently 90 mW/cm2 sensor 60 kW total tolerable? readout time: simulations on going 40 s total RO time (200 rows) has to be shortened limit near ~10 us 24 Detector Performance (Simulation) Detector simulation for pixels # of hit pixels vs. energy Relative RMS of # of hit pixels Energy projection from all layers in

case that two gammas are injected with 5mm separation. good separation capability this is conformed up to 2.5mm at least. Still under studying. 25 Letter of Intent Now, we are writing Letter of Intent. 1. Physics Motivation 2. Conceptual design of FOCAL 3. Mechanics 4. Electronics 5. Standalone performance 6. Performance in p+p, p+A, and Pb+Pb 7. Prototype and test results 8. Detector calibration and Monitoring 9. Time schedule 10. Cost estimation Participation is very welcome! 26 Preparation of beamtest Requesting FOCAL beamtest at CERN-PS/SPS Possible time slot:

T10 beamline in PS: 7-21. November (2011) H2 beamline (EHN1) in SPS (???) : Not fixed yet. Purposes: Evaluation of detector performances Compatibility to ALICE DAQ system/DATE format Readiness by then: One tower of W+ Si pad calorimeter and corresponding ASICs Plans for further downstreams (TRU/SRS) will be discussed. No main workers have been assigned. Partial of W+ MIMOSA pixel calorimeter 27 Summary Current FOCAL activities are reported. 2 major design candidates (and possible combination). Standard W+Si pad/Si strip in preshower configuration Simulation study and hardware development are on going. Full simulation in p+p/p+A was done and full simulation in A+A is needed. ASICs and Mechanics are under development. Development of digital parts (ADC/TRU/SRS) has not been started W+Si pixel configuration using MAPS techniques Simulation study and hardware development are on going. Basic performance is studied and full simulation will be done. Newly developed MIMOSA chip is under construction.

Letter of Intent is being written. Beamtest is planed around Nov. in 2011. Any participation is very welcome!! We eagerly need you! Backup slides Taku, Yasuto 37 Pi0 reconstruction using Si-Strips Two clusters in the Si-pads starts to merge into one cluster wh en the two-hit distance is below 2cm (for 1cm x 1cm pads) Locate a cluster with large energy deposit in the Si-pads & defi ne search region in the Si-strips Search for two clusters & obtain distance between the clusters First cluster 70GeV pi0 Second cluster 100GeV pi0 150GeV pi0 200GeV pi0 Mask area Strip position (/0.5mm) Status of ALICE FoCAL at ALICE Upgrade Forum on 2010/03/22

29 Taku, 20 ADC/TDC & FPGA board At least, 10 bit is not enough. More than 12 bit. Commercial FADC (TI, AD,,,) with multi-channel/chip, 10-5 0MSPS, low power consumption Roughly speaking, data size in p+A could be: 0.3(occupancy) x 256 (tower) x 64 x 3 (ch/tower ) x 2 (H/L) x 12 (bit) x 20 (# of samples) = 0.9MB/event Reference: dN/dy=700, 15MB/evt (TPC), 1.1MB/evt (TRD) Need to extrapolate to A+A FPGA (Xilinx Virtex series) for zero suppression, feature ext raction (online pulse shape analysis, summation), event b uilding, formatting, trigger input handing, output bufferin g (and send to SUR) Similar to TRU in PHOS/EMCAL. RD51, 21 FEE & SRU Use SRU as EMCAL/DCAL/(TPC) will do. developed by RD51+ALICE project TTCrx interface for trigger handling 10 GBE, SPF, optical fiber Master for the slow control

of FEEcards RD51, 22 Scheme: FEE and SRU Taku 23 Preamplifier Three different types of readout amplifier: Charge sensitive amplifier (CSA) Pad output current is integrated on the feedback capacitor in CSA. Best in terms of noise Voltage amplifier Pad output signal is integrated on the pad capacitance (Cd) and the voltage across the capacitor is amplified. Uniformi ty of Cd is necessary. Current amplifier Pad output signal is directly amplified and transformed into a voltage signal. Low input impedance and this limits the u se in systems with large capacitive loads Taku, ShinIchi, RIKEN 24 Dual charge sensitive preamplifier Due to the limited output swing of ASIC (5V, 3.3V, 2.5V d epending on process), dual input preamplifier with dual gain is designed. Requirements:

Open loop gain is sufficiently larger compared to the capacitan ce (Z = 1/wC + r/A, 1/wC >> r/A) Input impedance (Z) is sufficiently smaller compared to Cd 200pF Chigh 5.6nF Clow 560pF 10pF CSA CSA 10pF High side PZ Dual integrator (2nd shaper) PZ Dual integrator (2nd shaper) Low side ASIC CSA in high gain side has additional saturation avoidance circuit to keep the constant input impedance of high side.

Taku 26 Next plans including trigger capability Revisit our charge sensitive preamplifier To enlarge bandwidth, phase margin, open (closed) loop gain Another type of QTC without CMOS switches and shaper Design is underway. Another type of preamplifier Voltage amplifier proposed by Chuck (ORNL) Pad output signal is integrated on the pad capacitance (Cd) and the vol tage across the capacitor is amplified. Source follower at the 1st stage See Chuck and Davids slides shown in last week. Current amplifier Pad output signal is directly amplified and transformed into a voltage si gnal. Low input impedance and this limits the use in systems with large capacitive loads Taku 27 Voltage amplifier Shown by Chuck & David (ORNL) last week Quick simulation using LTSPICE (by Taku) Chigh 18pF Voltage at input gate

1.8pF CSA Output V (low side) 200pF Input current (5pC/100MIP) Clow 1.8pF Linearity (high/low) Output V (high side) 500ns CSA 1.8pF Taku 28 Current preamplifier LTSPICE simulation (Taku) Saturation avoidance circuit Input current (0.1pC-150pA)

High gain (R=1kohm) Low gain (R=0.1kohm) Output (high, 1kohm) (0.1pC-150pA) Fast signal processing! Output (low, 0.1kohm) (0.1pC-150pA) Fast signal processing! 100ns Taku 29 Linearity Linearity V=V(out)-V(baseline) Zin=10Ohm No gain optimization Good linearity is seen. high low

Need to optimize CMOS parameters (gm, W/L, I etc) and gain according to realistic conditions. One of the crucial issues is how large impedance the transmissi on line has. We are planning to use long line for raw signal driving (10cm). Conductance, capacitance, resistance should be carefully evaluated. Taku 30 QTCv2 QTC without CMOS switches (Taku) Constant current feedback by sensing the output voltage. V-I feedback circuit 1.8pF CSA Inclination is constant Inclination is constant Large gm High side 1pC 100pC (source follower +Cf = 1.8pC) 2u

Low side 1pC - 150pC (source follower + Cf=1.8pC) 2u 4u RIKEN 31 R&D of Dual CSP Chip size 1 mm 2 mm One channel for H/L. 0.5 mm pit status and Future plch lead Future pl 20mW/ch 1.8pF SA(high gain) Chigh Clow 7 mm 7 mm Qin (fC) 6 (= 136 keV) 0 12 1.8pF SA(low gain)

Clow = Chigh/10 18 Noise FWHM~90keV (S/[email protected]) Linearity : 10000 0.15 MeV 1.5GeV O Gert-Jan, 42 One layer, split in two halflayers one halflayer 1.5 mm W W is good heat conductor 170 W/mK (Al 240 W/mK) estimated heat resistance ~1 K/W no additional interconnect layer/ mounting board row of 4 chips (thinned to 120 um), glued to W row of 4 chips (thinned to 120 um), glued to W interconnect flex between chips comes here interconnect flex between chips comes here

GJN41 41 Gert-Jan, 43 One layer, split in two halflayers 1 layer = two halflayers mounted face to face 3 mm W 16 chips, their dead zones overlapping 4 flextails sticking out total thickness 1.5 + 0.5 +0.5 +1.5 mm further reduction towards 0.5 mm in total for sensors and cables seems possible, requires gluing all layers together 1 layer cooling pipes at sides will be inserted after assembly of tower these sides for cables tension rods keep stack together (prototype) first halflayer partially cut away showing overlap (grey and green chips) GJN42 42 Thomas, 45

Two gamma separation Event display Taku, 11 Another choice of design Readout individual layers. Amplification, shaping, digitizati on, serialization are done behind the wafer. Lower noise compared to raw signal driving on summing board a nd smaller dead space between towers. CMS preshower R. Poschl for the CALICE collab. Calor2010 conf. CMS preshower Forward Calorimeter: Silicon W Calorimetry Particle W: 2X0 3 layers (W + Si pad) X-Y Si pixel (3 layers) 0.3 mm thickness (x & y layer each)

Pixel size 0.5 mm * 0.5 mm x 6 mm W thickness = 3.5 mm 12 layers (W + Si pad) 2+3+1+3+1+12 = 22 X0 Si Pad + W(1X0) Si thickness Si size 0.3 mm 1 cm x 1cm W thickness 3.5 mm Only Tungsten (W) W thickness 3.5 mm 2. MAPS minitower for beam test 4 chips per layer: 2*19.2 mm in X, 2* 19.2 mm in Y estimated RM = 14 mm

prototype chip PHASE1/MIMOSA23 testchip for STAR upgrade in production test electronics developed in Berkeley 640 * 640 pixels 30 um pitch read-out time 0.6 ms no on-board data reduction read-out system chips wire bonded to conventional flexes modified version of test board for 100 chips 3 Dec 10 Upgrade Forum GJN46 MAPS prototype read-out System Architecture Virtex6 FPGA Board + Adapter 4 Layers of 4 Mimosa sensors for 1 Board 4*7 RJ45 Connectors, LVDS Signals SIU + TTC Connectors

6 sets of electronics needed for one detector tower. Det ect or Tower Adapt er B U F F E R H P C RJ45 45 RJ 45 RJ 45 RJ RJ 45 RJ 45 RJ 45 8*4 L P C

8 SI U 8 2 TTC Cl k/ Trg Vi r tex6 FPGA BRD Opt i cal DAQ PC El ect roni cs Si de Dat a J TAG CLOCK RSTB Fl ex Cabl e Detect or Si de Up t o 4 l ayers f or 1 FPGA Board

VDD/ VDDA/ V_CLP Power Count i ng Room Bergen MAPS prototype read-out Virtex6 FPGA Board Communications and Networking 10/100/1000 Tri-Speed Ethernet More than 100 LVDS signals SFP transceiver connector Memory for data buffering USB Host Port and USB Peripheral Port DDR3 SO-DIMM (512 MB) PCI Express x8 Edge Connector Software development environment was setup. Two FMC Connectors Hardware tests are going on. Readout firmware and software under construction. Bergen MAPS prototype read-out

Adapter Board Schematic design finish ed. Beginning to layout soo n. Adapt er Board TTC LVDS 34 LVDS Cl ock 2 MGT 1 MGT Cl ock 1 Power, gnd L P C SI U 8

Data FMC 32 12 Layer 1 FMC CTRL 8 Power, gnd 8 8 32 4 layers separately configured and read out Sensors of the same layer working synchro

nously with the same configuration. LVDS Signals with Buffering RJ45 Connectors Analog input for system monitoring. Configurable SIU and TTC connections Spare IOs for single chip test. Buffer LVDS 78 2 LVDS Cl ock LVDS Cl ock 2 MGT 8 MGT Cl ock 2 Power, gnd RJ 45 RJ 45

RJ 45 RJ 45 8 32 H P C 13 8 5 Buffer LVTTL | LVDS Dat a1 8 8 Dat a3

Dat a4 8 RJ 45 8 8 RJ 45 8 2 RJ 45 8 8 Dat a2 8 Cl ock/ Cont rol / Moni t ori ng

J TAG RSTB, GND Anal og Layer 2 Layer 3 Layer 4 Bergen Diagram of new scheme Det ect or Layer 7 Det ect or Layer 6 Det ect or Layer 8 Det ect or Layer 5 Det ector Layer 9 Det ect or Layer 4 Det ect or Layer 10 Det ect or Layer 3 Det ect or Layer 11 Det ect or Layer 2 Det ect or Layer 12 Det ect or Layer 1 Dat a

SP6 FGG676 +12V, 5A 640Mbps * 24 *2 Spart an6 FPGA +5V, 10A 3. 3V I O SP6 FGG676 2. 5V I O x J TAG RS232 Red:Top Blue:Bottom Two layers of connection board All for 1 tower fits in a 19/2 U crate. First data sparsification in Sp

artan6. Data buffering and transmiss ion with Virtex6. More functionality and flexi bility, higher density, lower c ost. Schematics finished, layout i n progress, to be finished in 2 weeks. Power Suppl y LAN Full speed data flow into tw o Spartans: DVI AC 640Mbps/MAPS * 24 * 2 32Gbps. Consol e 19 crate 18 Feb 11 Upgrade Forum Shimin Yang

GJN50 Virtex 6 dev-board Petalinux evaluated Beginning to cross compile existing code for petalinux Commercially available Linux distribution for Virtex 6 Existing command line interface Software for access to registers of the firmware PLB bus in Microblaze core used for now, gives small interface i ssue, but should be solved soon. Plan to use AXI bus when there is better PetaLinux support. Software side joined by Hgskolen i Vestfold 18 Feb 11

Upgrade Forum GJN51

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