Programmed IO Direct memory access (DMA) Memory mapped IO Interrupts Programmable Interrupt controller Interfacing devices to CPU via interrupts 02/09/20 2 Internal Architecture of a CPU (Z80) 02/09/20 3 Fetch and Execute Cycles
Macro instructions are fetched from memory and executed. Fetch and execute cycles: simple overlap. 02/09/20 4 Microcontroller approach (fig.2.7) Microcontroller is a internal processor that is programmable via microinstructions. This approach is highly relevant to real-time systems and devices since
each macro instruction is mapped into a set of microinstructions that can be directly executed with decoding etc. Fine grained instructions are in micro memory and are wider than macro instructions. These microinstructions directly control the logic gates of the microcontroller. Microcontroller can take direct input from devices and can signal directly to devices. High level language support is available for software development using microcontrollers. Examples: Intel 8051, 8748, MCS 51/251 See http://www.intel.com/design/embcontrol/index.htm 02/09/20 5 Instruction formats
1, 0 address forms (implicit operands, destination); example: pop 2-address forms: arithmetic operations 3-address forms Core instructions: Horizontal bit operations: XOR, AND, NOT Vertical bit operations: rotate right, rotate left Control: trap, cli, epi, dpi, halt Data movement: store/load Math/special processing: add, sub, bts (lock) 02/09/20 6 Addressing Modes Immediate Direct memory Indirect memory Register Auto-increment, auto-decrement
02/09/20 7 RISC vs CISC CISC (complex instruction set computer) Complex instructions: multiple cycles Any instruction can ref memory No instructions are pipelined Micro-program for native instruction Variable format instructions Multiple instructions and addressing mode Single set of registers Complexity is in the micro-program and hardware 02/09/20 8
RISC vs. CISC RISC (reduced instruction set computer) Complementary set of first eight CISC principles Simple single cycle instructions Load/store only can reference memory Highly pipelined Instructions directly executed by hardware Fixed-format instructions
Few instructions and addressing modes Large multiple set of registers Complexity handled by the compiler and software Advantage for real-time system: average instruction execution time is lower than cisc Disadvantage: associated with cache and elaborate multistage pipeline, while this improves performance for average case, pathological (extreme) situations may not be handled satisfactorily. Many real-time systems typically encounter extreme conditions. 02/09/20 9 Memory Memory access time: interval between when a datum is requested and when it is available to
the CPU. This can have profound effect on real-time performance. Real access time is decided by the physical characteristic of the memory chosen. Effective access time depends on type, memory technology, memory layout (ex: memory interleaving), and buffering etc. 02/09/20 10 Memory Access Typical microprocessor read cycle embodies the handshaking between the processor and main memory store. 1. 2. 3. 4. 5.
CPU places address on address bus and allows signal to settle. Then it places appropriate data on the data bus. CPU asserts ALE (Address Latch enable) CPU sends out WR signal Memory device is selected and the data is written to the addressed location All are synchronized to the system clock. 02/09/20 11
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