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February 25, 2020W65C02S8–bit MicroprocessorWDC reserves the right to make changes at any time without notice in order to improve design and supplythe best possible product. Information contained herein is provided gratuitously and without liability, to anyuser. Reasonable efforts have been made to verify the accuracy of the information but no guaranteewhatsoever is given as to the accuracy or as to its applicability to particular uses. In every instance, it mustbe the responsibility of the user to determine the suitability of the products for each application. WDCproducts are not authorized for use as critical components in life support devices or systems. Nothingcontained herein shall be construed as a recommendation to use any product in violation of existing patentsor other rights of third parties. The sale of any WDC product is subject to all WDC Terms and Conditions ofSales and Sales Policies, copies of which are available upon request.Copyright 1981-2020 by The Western Design Center, Inc.reproduction, in whole, or in part, in any form.All rights reserved, including the right of

TABLE OF CONTENTS1INTRODUCTION . 51.12FUNCTIONAL DESCRIPTION . 62.12.22.32.42.52.62.72.83ADDRESS BUS (A0-A15) . 9BUS ENABLE (BE) . 9DATA BUS (D0-D7) . 9INTERRUPT REQUEST (IRQB). 9MEMORY LOCK (MLB) . 9NON-M ASKABLE INTERRUPT (NMIB) . 9NO CONNECT (NC) . 9PHASE 2 IN (PHI2), PHASE 2 OUT (PHI2O) AND PHASE 1 OUT (PHI1O) . 10READ/WRITE (RWB) . 10READY (RDY) . 10RESET (RESB) . 10SET OVERFLOW (SOB) . 11SYNCHRONIZE WITH OPCODE FETCH (SYNC) . 11POWER (VDD) AND GROUND (VSS) . 11VECTOR PULL (VPB) . 11ADDRESSING MODES . .154.165INSTRUCTION REGISTER (IR) AND DECODE . 6TIMING CONTROL UNIT (TCU) . 6ARITHMETIC AND LOGIC UNIT (ALU) . 6ACCUMULATOR REGISTER (A). 6INDEX REGISTERS (X AND Y) . 6PROCESSOR STATUS REGISTER (P) . 6PROGRAM COUNTER REGISTER (PC) . 7STACK POINTER REGISTER (S). 7PIN FUNCTION DESCRIPTION . 154FEATURES OF THE W65C02S . 5ABSOLUTE A. 15ABSOLUTE INDEXED INDIRECT (A,X) . 15ABSOLUTE INDEXED WITH X A,X . 15ABSOLUTE INDEXED WITH Y A, Y. 16ABSOLUTE INDIRECT (A) . 16ACCUMULATOR A . 16IMMEDIATE ADDRESSING # . 16IMPLIED I . 17PROGRAM COUNTER RELATIVE R . 17STACK S . 17ZERO PAGE ZP . 17ZERO PAGE INDEXED INDIRECT (ZP,X) . 18ZERO PAGE INDEXED WITH X ZP,X . 18ZERO PAGE INDEXED WITH Y ZP, Y . 18ZERO PAGE INDIRECT (ZP) . 18ZERO PAGE INDIRECT INDEXED WITH Y (ZP), Y . 19OPERATION TABLES. 212

6DC, AC AND TIMING CHARACTERISTICS . 236.26.3DC CHARACTERISTICS TA -40 C TO 85 C (PLCC, QFP) TA 0 C TO 70 C (DIP) . 24AC CHARACTERISTICS TA -40 C TO 85 C (PLCC, QFP) TA 0 C TO 70 C (DIP) . 257CAVEATS . 308HARD CORE MODEL . 318.19FEATURES OF THE W65C02S HARD CORE MODEL . 31SOFT CORE RTL MODEL . 319.1W65C02 SYNTHESIZABLE RTL-CODE IN VERILOG HDL . 3110 ORDERING INFORMATION . 323

TABLE OF TABLESTABLE 3-1TABLE 3-2TABLE 4-1TABLE 5-1TABLE 5-2TABLE 6-1TABLE 6-2TABLE 6-3TABLE 6-4TABLE 7-1VECTOR LOCATIONS . 12PIN FUNCTION TABLE . 12ADDRESSING MODE TABLE . 20INSTRUCTION SET TABLE . 21W65C02S OPCODE MATRIX . 22ABSOLUTE MAXIMUM RATINGS . 23DC CHARACTERISTICS . 24AC CHARACTERISTICS . 25OPERATION, OPERATION CODES AND STATUS REGISTER . 27MICROPROCESSOR OPERATIONAL ENHANCEMENTS . 30TABLE OF FIGURESFIGURE 2-1FIGURE 2-2FIGURE 3-1FIGURE 3-2FIGURE 3-3FIGURE 6-1FIGURE 6-2FIGURE 6-3W65C02S INTERNAL ARCHITECTURE SIMPLIFIED BLOCK DIAGRAM . 7W65C02S MICROPROCESSOR PROGRAMMING MODEL . 8W65C02S 40 PIN PDIP PINOUT . 13W65C02S 44 PIN PLCC PINOUT. 13W65C02S 44 PIN QFP PINOUT . 14IDD VS VDD . 24F MAX VS VDD . 24GENERAL TIMING DIAGRAM. 264

1 INTRODUCTIONThe W65C02S is a low power cost sensitive 8-bit microprocessor. The W65C02S is a fully static coreand the PHI2 clock can be stopped when it is in the high (logic 1) or low (logic 0) state. The variablelength instruction set and manually optimized core size makes the W65C02S an excellent choice for lowpower System-on-Chip (SoC) designs. The Verilog RTL model is available for ASIC design flows. WDC,a Fabless Semiconductor Company, provides packaged chips for evaluation or volume production. To aidin system development, WDC provides a software development suite (WDCTools).You can find out more about our development hardware tools ng-development-system/And software tools here:https://wdc65xx.com/WDCTools1.1Features of the W65C02S 8-bit data bus16-bit address bus provides access to 65,536 bytes of memory space8-bit ALU, Accumulator, Stack Pointer, Index Registers, Processor Status Register16-bit Program Counter70 instructions16 addressing modes212 Operation Codes (OpCodes)Vector Pull (VPB) output indicates when interrupt vectors are being addressedWAit-for-Interrupt (WAI) and SToP (STP) instructions reduce power consumption, decreaseinterrupt latency and provide synchronization with external eventsVariable length instruction set provides for lower power and smaller code optimization over fixedlength instruction set processorsFully static circuitryWide operating voltage range, 1.8 /- 5%, 2.5 /- 5%, 3.0 /- 5%, 3.3 /- 10%, 5.0 /- 5% specifiedLow Power consumption, [email protected]

2 FUNCTIONAL DESCRIPTIONThe internal organization of the W65C02S is divided into two parts: 1) Register Section and 2) ControlSection. Instructions obtained from program memory are executed by implementing a series of datatransfers within the Register Section. Signals that cause data transfers are generated within the ControlSection.2.1Instruction Register (IR) and DecodeThe Operation Code (OpCode) portion of the instruction is loaded into the Instruction Register from the DataBus and is latched during the OpCode fetch cycle. The OpCode is then decoded, along with timing andinterrupt signals, to generate various control signals for program execution.2.2Timing Control Unit (TCU)The Timing Control Unit (TCU) provides timing for each instruction cycle that is executed. The TCU is setto zero for each instruction fetch, and is advanced at the beginning of each cycle for as many cycles as isrequired to complete the instruction. Data transfers between registers depend upon decoding thecontents of both the IR and the TCU.2.3Arithmetic and Logic Unit (ALU)All arithmetic and logic operations take place within the ALU. In addition to data operations, the ALU alsocalculates the effective address for relative and indexed addressing modes. The result of a data operationis stored in either memory or an internal register. Carry, Negative, Overflow and Zero flags are updatedfollowing the ALU data operation.2.4Accumulator Register (A)The Accumulator Register (A) is an 8-bit general purpose register which holds one of the operands and theresult of arithmetic and logical operations. Reconfigured versions of this processor family could haveadditional accumulators.2.5Index Registers (X and Y)There are two 8-bit Index Registers (X and Y) which may be used as general purpose registers or to providean index value for calculation of the effective address. When executing an instruction with indexedaddressing, th